This invention relates to a dynamic random access memory cell using field effect devices.
Volatile random access semiconductor memories have been built using bipolar and MOS silicon transistors. Static semiconductor memories use flip-flop or cross-coupled inverters composed of bipolar or MOS transistors for each memory cell resulting in a memory that will hold the information in the memory cell so long as power supply voltages are maintained. There are also known memory cells, referred to as dynamic memories, in which the information is held in the memory cell by a charge capacitor which may be in the form of a capacitor or an expanded gate, source or drain electrode of a field effect transistor.
One common form of memory cell using field effect transistors comprises a pair of load transistors having their drain connected to a direct current bias source, a pair of directly cross-coupled active transistors, and a pair of access transistors. The three transistors of each half of the cell have a common junction point. The access transistors have their gate electrodes connected together to a word line, and the other electrodes of the two transistors connected respectively to two complementary conductors of a data bit line. Examples are shown in U.S. Pat. No. 4,175,290 by Hanani, referring to U.S. Pat. No. 3,831,155 and to a conference article by F. Schuermeyer and C. Young. Another example is shown in U.S. Pat. No. 4,044,343 by Uchida.
At present, Schottky Barrier (or metal semiconductor) field effect transistor technology has been developed. GaAs devices are used to obtain high speed operation. This technology uses depletion mode devices. Consequently the use of this technology requires level shift circuits which consume surface area, power, and which contribute to the delay of the circuit. The conventional level shift circuits use diodes in conjunction with current sources. Two level shift circuits would be required for every random access memory (RAM) cell. No GaAs random access memory cell has been reported.